An apparatus containing a processor may have different modes of operation, the different modes representing a different trade-off between power consumption and performance.
In one exemplary mode of operation (“performance” mode), internal resources of the apparatus, including the processor, may be operated for high performance that may result in high power consumption.
In another exemplary mode of operation (“power-save” mode), internal resources of the apparatus, including the processor, may be operated for low power consumption while maintaining a predetermined performance for this mode of operation.
A processor may comprise a core constrained to have a lowest of core clock signal frequencies no lower than a predetermined multiple of a lowest of bus clock signal frequencies of a bus coupled to the processor. As higher bus clock signal frequencies become possible, this raises the lower limit to which the core clock signal frequencies can be reduced in power-save mode, thus hampering the efforts to reduce power consumption in power-save mode.
It would be beneficial to reduce power consumption while the apparatus operates in power-save mode, while maintaining or improving the performance.